The present subject matter relates to a semiconductor design technology, and more particularly, to a data output circuit for outputting internal information data such as a vendor ID through an input/output pad.
In general, a semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) provides internal information data to an external device such as a chip set through an input/output pad. For example, the internal information data includes a vender ID for identifying a manufacturing company of a semiconductor memory device, and the semiconductor memory device includes a register for storing such a vender ID. If a semiconductor memory device includes additional pads for outputting a vender ID, the number of pads increases as many as the additional pads, and a manufacturing cost thereof increases, too. Therefore, the vender ID is outputted through an input/output pad.
FIG. 1 is a circuit diagram illustrating a data output circuit according to the related art.
Referring to FIG. 1, the data output circuit includes a serial data output unit 110, a buffer 130, and a data selection and output unit 150.
The serial data output unit 110 serializes 0th to 3rd output data D_OUTB<0:3> which are parallel data and outputs serial data MUXOUTB. Here, the serial data output unit 110 includes an internal data input unit 112, an activation unit 114, and a power supply unit 116.
The internal data input unit 112 receives 0th to 3rd output data D_OUTB<0:3>. The internal data input unit 112 includes a plurality of NMOS transistors for receiving each of 0th to 3rd output data D_OUTB<0:3>.
The activation unit 114 controls an activation operation of the internal data input unit 112 in response to a sub power down mode signal PWDNB. The activation unit 114 includes a plurality of NMOS transistors disposed between the internal data input unit 112 and a ground power supply end VSS. The sub power down mode signal PWDNB is a signal activated in a mode to minimize power used in a semiconductor memory device. Such a mode is referred to as a power down mode, hereinafter.
The power supply unit 116 supplies power to an output node A and includes a plurality of PMOS transistors connected between an external power supply end VDD and the output node A.
The buffer 130 buffers a signal generated at the output node A and outputs the buffered signal as serial data MUXOUTB.
The data selection and output unit 150 outputs serial data MUXOUTB or vender ID data ID_DAT to an output end OUT in response to the sub power down mode signal PWDNB and a main ID activation signal IDEN. Data outputted to the output end OUT is outputted to an input/output pad (not shown) through a pre-driver (not shown) and a main driver (not shown).
The sub power down mode signal PWDNB becomes a logic ‘high’ in a read operation mode and becomes a logic ‘low’ in the power down mode. The main ID activation signal IDEN becomes a logic ‘high’ in a mode to output a vender ID (hereinafter, an ID output mode), and becomes a logic ‘low’ in the other modes except the ID output mode. In general, the ID output mode is performed in the power down mode. In other words, the data selection output unit 150 outputs the serial data MUXOUTB to the output end OUT in the read operation mode and outputs the vender ID data ID_DAT to the output end OUT in the ID output mode.
Hereinafter, a problem of a data output circuit according the related art will be described as follows.
The data output circuit according to the related art includes a data selection and output unit 150 for selectively outputting the serial data MUXOUTB and the vender ID data ID_DAT through one input/output pad (not shown). While the data selection and output unit 150 includes first to third NAND gates NAND1, NAND2, and NAND3, the first NAND gate NAND1 and the second NAND gate NAND2 operates as loading with respect to the serial data MAXOUTB. Such loading may be a factor that deteriorates high speed operation in outputting the serial data MUXOUTB to the input/output pad. Furthermore, the higher the operation frequency of the semiconductor memory device becomes, the more timing jitter increases due to inter symbol interference (ISI).